1. Field of the Invention
The present invention relates to a circuit design assisting apparatus, a circuit design assisting method, and circuit design assisting program, and in particular to circuit designing capable of satisfying a signal requirement in an integrated circuit.
2. Discussion of the Background Art
When a semiconductor integrated circuit, especially a chip, mounting a hard macro, such as a RAM, a ROM, a CPU, a PHY, etc., is designed, the hard macro is needed to operate as specified. Because, it is common to design a semiconductor integrated circuit using an existing hard macro.
As a specific consideration factor in designing the semiconductor integrated circuit, a signal having a shorter transition time period than that supposed by a specification needs to be input to an input terminal of a hard macro. Further, a circuit (cell) having a smaller load capacity than that supposed by a specification needs to be connected to an output terminal of a hard macro. Thus, a conventional circuit design-assisting tool describes a design requirement, such as a maximum transition time permissible for an input terminal, a maximum load capacity driven by an output signal of the output terminal, etc., as specification information of the hard macro. Then, designing is executed meeting the requirement.
As a circuit design-assisting tool, the following has been proposed. For example, a length of wiring of scan chain data is calculated based on a net list and layout data outputted based on a weighting coefficient of wiring. The weighting coefficient is then changed in accordance with the calculation result. The Japanese Patent Application Laid Open No. 2006-323638 attempts to reduce scan chain wiring differently.
However, even the above-mentioned circuit design assisting tool is utilized, all of applicable devices does not satisfy the requirement. For example, when plural RAMs are arranged side by side, a length of wiring that connects terminals of the RAMs of the same voltage becomes longer due to a restriction on a cell arrangement space, and accordingly, the requirement cannot be satisfied. To solve such a problem, a buffer cell having an appropriate driving performance is connected to a terminal, which possibly raises such a problem, before a layout is executed by a circuit design assisting tool. Specifically, the layout is executed while positioning the buffer cell in the vicinity of the terminal of the hard macro raising the problem as closer as possible.
As a result, an operator needs to manually create a net list by inserting the buffer cell. A correspondence list listing a correspondence between terminals of the hard macro and buffer cells forcibly arranged in the vicinity of the terminals also needs to be manually created. Accordingly, when a number of hard macro or that of terminals increases, labor of the above-mentioned operation significantly takes a long time. In addition, an erroneous operation highly probably occurs. Further, confirmation of operation result needs a long time.